Microprocessor design often incorporates, integrated on a single semiconductor chip in one form or another, one or more storage units to be used for temporarily storing digital information. One type of storage commonly used is a dynamic random access memory (RAM). For various reasons which will be recognized by those skilled in this art, RAM type memory brings with it certain disadvantages which, when the microprocessor and accompanying memory is to be implemented in integrated circuit form, make it desirable to look for other types of temporary storage. For example, dynamic RAM often will require more semiconductor area for implementation.
Another type of temporary storage element for microprocessor use is a static latch. Latches are used in favor of RAM storage in isolated, distributed locations throughout the architecture of the microprocessor or such as, for example, as temporary data storage at inputs or outputs of various elements. One implementation of a latch uses a pair of inverter circuits and a feedback path coupling the output to the input for each individual "cell" (i.e., single-bit storage), thereby "latching" the information applied to the input. This type of latch, commonly known as a "static latch," is often found in complementary metal-oxide-silicon (CMOS) microprocessor implementation, and includes a transfer gate, operable in response to a strobe signal, to transfer data from a data line to the input stage for latching. The transfer gate may be formed from an N-channel MOS transistor and a P-channel MOS transistor coupled in parallel (i.e., their respective source and drain leads connected together), the respective gate leads of each transistor being adapted to receive the strobe signal and its complement. One disadvantage to this type of transfer gate is that signal line pairs must conduct the strobe signal and its complement to each transfer gate, resulting in a significant semiconductor-area penalty in the integrated circuit layout of each static latch used.
A partial solution is to eliminate one of the MOS transistors (usually the P-channel transistor). Thereby, the remaining transistor used to implement the transfer gate needs only the strobe signal or its complement, not both, to operate. Thus, deletion of one strobe line is accomplished, accompanied by a decrease in semiconductor area required for formation of the latch. Unfortunately, two problems occur in this implementation: First, where a logic "1" is stored in the latch cell and a logic "0" is being written, the feedback device (usually a single MOS transistor connected to operate in a depletion mode) can be placed in a gate overdrive condition, resulting in the transfer gate having to be excessively large enough to handle the current created by this situation. This, in turn, requires more semiconductor area to form the transistor of the transfer gate.
In the alternative case, involving a logic "0" stored and a logic "1" being written, the transfer gate transistor must supply enough current to both charge the input node and to supply current to the feedback device. Often there can be a problem attempting to pull the voltage up to reach the trip point of the latch cell input during the time period allotted by the strobe signal. The transfer gate transistor is operating, in this circumstance, in a voltage follower mode in which the current therethrough decreases as a square law function when the source lead of the transfer gate transistor is pulled to a "1" voltage level. The situation is ascerbated by the fact that the feedback transistor forming the feedback path of the latch is on. Thus, as the input voltage to the latch rises, the current necessary to charge the capacitance of the input node of the latch decreases considerably.
It can be seen, therefore, that while the use of static latches in semiconductor design have advantages over use of RAM elements, such use can affect microprocessor design insofar as the amount of semiconductor area needed to implement the latch circuits vis-a-vis the remainder of the microprocessor, a major concern of any integrated semiconductor circuit design.